There is a new era started in verification in terms of having the Verification IP (VIP) used for verification! Verification IP has simplified the way in which verification carried out of any complex DUT’s! Verification IPs (VIPs) can be developed in System Verilog, System C Or UVM! These VIP’s are worth millions of dollars in terms of license coasting to the customers! These are developed by premier companies like Cadence, Synopsys, Mentor Graphics and PerfectVIPs! There are Verification VIPs to verify PCIe, USB, SATA, SAS, Fiber Channel and Ethernet Protocols are available in the market!
These Verification IPs (VIPs) developed with special verification features which make them unique compared to other verification techniques! Verification IPs (VIP) has most important feature in terms of having the in-built error injection and flexibility in configuration which help finding the complex bugs in design! Error injection is done through callbacks, factory methods or special monitor features which allow them to corrupt any outgoing transactions! These callbacks capture transactions going on to the bus and corrupts it before reaching the design! There are other mechanisms like active bus monitors which can corrupt the transactions going on an interface!
Verification IPs (VIP) are developed with various configuration to verify various aspects of design! Same Verification IP can work in various modes! These kinds of configurations mechanism allow same Verification IP to work in different mode! Example, PCIe Verification IP VIP can be configured to work as switch, endpoint, or root complex with configuration parameters! It makes integration and verification of various design in simple ways! It makes testbench development simpler compared to any other modes of verification!
Another important feature of (Verification IP) VIP is inbuilt developed protocol violation checkers! There is monitor integrated on interface between Design and Verification IP! It can be used to monitor transactions on bus and can be used to verify protocol rules automatically! Also, protocol rules can be developed as part of verification IP! Whenever any transactions are sent or received from DUT then in-built protocol checkers developed in Verification IP can trigger error on protocol violation! Verification IP can throw errors which are mapped to specification and can help verification engineers to file bugs against design specification easily without knowing the protocol specification without any detail! This method can provide protocol checking on each transaction! Example, PCIe protocol violations can be implemented as part of protocol checker from specification as part of Verification IP! It can check for protocol rules mapped to specification on an every TLP and DLLP received from design! It can pinpoint design bugs to designers! Designers can fix those kinds of bugs mapped to specification easily!
Apart from it, Errors can be reported with various verbosity to verification engineers and debuggers using Verification IP feature. We can mask or demote any errors or protocol violations in case of those are known design issues. Also, we can configure Verification IP(VIP) to bypass or enable/disable any flow if its not supported by design. Example, we can bypass LTSSM in PCIe Verification IP if it’s not implemented in PCIe design. It can be very important feature which can help designers to verify design at an earlier stage before completing the design.
Overall, In Modern era Verification IP provides many features which can be useful to verify the design. It comes with features like error injectors, protocol checkers, various configurations, and ease of test bench development. Now a days, Every MNC uses Verification IP to verify their design and find bugs faster with ease.
