PCIe Basic Course(Gen1 to Gen5) Demo Video

Overview

PCIe Basic Course is a 6-7 week course (Weekend Training Only). It covers all the aspects of  PCIe Gen1 to Gen5, including PCIe topology, Configuration Space, Enumeration, Transaction Layer, Data Link Layer, Physical Layer, Interrupt Handling, Error Handling, Power Management, System Architecture and PIPE Interface. Course also includes the PCIe SoC Level Test plan discussions.

Syllabus

A) Introduction
  • PCI Express Link
  • PCI Express Fabric Topology
  • PCI Express Layering Overview

 B) Transaction Layer Specification

  • Transaction Layer Overview
  • Transaction Layer Protocol – Packet Definition
  • Handling of Received TLPs
  • Transaction Ordering
  • Virtual Channel (VC) Mechanism
  • Ordering and Receive Buffer F

C) Data Link Layer Specification

  • Data Link Layer Overview
  • Data Link Control and Management State Machine
  • Data Link Feature Exchange
  • Flow Control Initialization Protocol
  • Data Link Layer Packets
  • Data Integrity

D) Physical Layer Logical Block

  • Introduction
  • Logical Sub-block
  • Link Initialization and Training
  • Retimers

E) Power Management

  • Overview
  • Link State Power Management
  • PCI-PM Software Compatible Mechanisms
  • Native PCI Express Power Management Mechanisms
  • L1 PM Substates
  • Auxiliary Power Support
  • Power Management System Message and DLLPs
  • PCI Function Power State Transitions
  • Function Power Management Policies
  • PCI Bridges and Power Management
  • Power Management Events

f) System Architecture

  • Interrupt and PME Support
  • Error Signaling and Logging
  • Virtual Channel Support
  • Device Synchronization
  • Locked Transactions
  • PCI Express Reset – Rules
  • PCI Express Hot-Plug Support
  • Power Budgeting Capability
  • Slot Power Limit Control
  • Root Complex Topology Discovery
  • Link Speed Management
  • Access Control Services (ACS)
  • Alternate Routing-ID Interpretation (ARI)
  • Multicast Operations
  • Atomic Operations

G) Software Initialization and Configuration

  • Configuration Topology
  • PCI Express Configuration Mechanisms
  • Configuration Transactions Rules
  • Configuration Register Types
  • PCI and PCIe Capabilities Required by Base Spec for all Ports
  • PCI Express Extended Capabilities
  • PCI and PCIe Capabilities Required by the Base Spec
  • MSI Capability Structure
  • MSI-X Capability and Table Structure
  • Secondary PCI Express Extended Capability
  • Data Link Feature Extended Capability
  • Physical Layer 16.0 GT/s Extended Capability
  • Lane Margining at the Receiver Extended Capability
  • Advanced Error Reporting Capability
  • Multi-Function Virtual Channel Capability

H) PCIe Enumeration

  • Link up Event
  • Physical Function Topology Discovery
  • Device Type Discovery
  • BAR Address Programming
  • Enabling the initial configuration

I) PCIe PIPE Interface

  • Introduction
  • PHY/MAC Interface
  • Original PIPE Architecture
  • Serdes Architecture
  • PIPE Interface Signal Descriptions

Schedule

Course
PCIe Basic Course(Gen1 to Gen5)
Duration
6-7 weeks(Weekends only training)
Next  Batch
10/12/2022
Demo Session
10/12/2022
Registration
03/12/2022
Schedule
Both Saturday & Sunday(Timings will be discussed after demo session)
One Session Duration
3 hours
Mode Of Training
Online Training In Skype
Batch Size
30-40 members
Assignments
TL, DL, and PL Assignments
Fees
Contact +91 9979601313 on-call or WhatsApp for fees details. Also, You can send the query by filling out the Course Enquiry form on the Contact US page.
Course Recordings
Every session recordings are available on skype for 30 days.
Prerequisites
B.Tech or M.Tech in Engineering
Trainer
7 Years of Experience in PCIe SoC and IP Level Verification.

Course Material

  • PCIe PPTs Presented During The Course
  • PCISIG PCIe Gen3 and Gen4 Specification
  • PCIe Mindshare Book
  • PCIe TL Layer, DL Layer, PL Layer and System Architecture Assignments
  • PCIe Interview Questions
  • PCIe SoC Level Verification Testplan

Trainer Profile

  • Trainer has 7 years of experience in PCIe Gen3, Gen4 and Gen5 IP and SoC Level Verification.
  • Trainer has worked in big MNCs like Intel, AMD and Synopsys in Functional Verification.